A low-cost architecture for multi-mode Reed-Solomon decoder
Yun Chen, Yuebin Huang, Wei Meng, Zhiyi Yu, Xiaoyang Zeng · 2012
This paper presents a multi-mode Reed-Solomon (RS) decoder with folding architecture which has low cost and low power consumption. The solution can be applied into any application that requires multi-mode RS codes. Implemented by SMIC 0.13 μm 1.2 V CMOS technology, the decoder runs at 440MHz clock rate and has a gate count of 65K and die size of 1.18×1.18 mm2. The power consumption is 0.25mW per error byte benefiting from the proper mode control, which is quite economical for a multi-mode RS decoder. The maximum error correction capability of the decoder is 32 bytes.