A VLSI 128-processor chip for multiresolution image processing
Maria Grazia Albanesi, Virginio Cantoni, Marco Ferretti, F. Mainieri · 2002
This paper presents the design of a multiprocessor chip integrating 128 simple processors arranged as a mesh of 8 rows by 16 columns. This mesh of PEs is intermingled with a dual mesh of switching elements, that interconnect the PEs and reconfigure them into one of three topologies. i) an 8-connected standard mesh, ii) a set of 4-connected independent meshes: iii) a quad-tree. This architecture is a viable solution to the problem of embedding into silicon a quad-pyramid, a well known multi-resolution structure for image processing. Local memory is shared between PEs of the same row and the address space increases with the level of the pyramid. The embedding supports fault-tolerance by column substitution.>