A 32-bit low power RISC core for embedded applications
Sung Ho Kwak, Seung Ho Lee, Byeong-Yoon Choi, Moon Key Lee · 2002
This paper describes a microprocessor that has been designed for embedded and portable application. This RISC processor offers very low power consumption and fast context switching. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40 MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with 0.6 /spl mu/m triple metal CMOS technology and consists of about 70 K transistors. The power dissipation is 140 mW.