Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation
Lien-Fei Chen, Shien-Yu Huang, Chi-Yao Liao, Yeong-Kang Lai · 2009
In this paper, a hardware efficient coarse-to-fine fast algorithm for H.264 motion estimation is proposed. We present hardware friendly two-step searching flow to obtain the 41 MVs of the variable block size motion estimation (VBSME) efficiently. At the first step, the candidate block down-sampling technique and the multi-level successive elimination algorithm (MSEA) with fixed 16 times 16 block-matching are adopted to rapidly find the possible regions. Then, the local full search method with VBSME is utilized at these possible regions to parallel calculate the minimum SAD of the 41 MVs. According to the analysis, proposed fast algorithm not only has 5% computational complexity compared with the full search block-matching algorithm (FSBMA), but also preserves fine RD performance. In the light of our hardware evaluation, the proposed fast algorithm can easily achieve the real-time HDTV video coding requirement with the 64 processing elements (PEs) architecture.