A new test pattern generator for high defect coverage in a BIST environment
Costas Laoudias, Dimitrios Nikolos · 2004
In this paper we propose a new Test Pattern Generator (TPG) for the detection of realistic faults occurring in CMOS nanometer technologies. The proposed TPG compares favorably to the corresponding already known TPGs with respect to the fault coverage obtained by test sequences of the same length. Another advantage of the proposed TPG is that the same TPG can be used for testing more than one modules in a SOC.