80960-next generation
G. Hinton · 2003
A discussion is presented of the next generation core for the 80960 family of embedded processor chips. It is shown that the next generation 960 core incorporates several features for high performance. It has wide and concurrent internal buses. It can decode and issue a sustained two instructions per clock even with loads and branches. It implements branch lookahead with branch prediction to minimize pipeline breaks. It manages the parallelism and multiple functional units by using resource scoreboarding techniques. It is a modular, high-performance core designed for the embedded processor market. The goals of the core design, the basic microarchitecture, the pipeline, and the key performance features are examined.>