A VLSI architecture for arithmetic coding of multilevel images
M. Bóo, J.D. Bruguera, Thomas A. Lang · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1998
We describe a VLSI architecture of an arithmetic coder for a multilevel alphabet (256 symbols) that includes the storing and updating of probabilities, the updating of the interval, and the correction of the codeword. The architecture is based on the utilization of redundant arithmetic, and the development of new schemes for storing and updating the cumulative probabilities and updating the range and left point of the current interval. The proposed implementation is compared with one that does not include these improvements, and is shown to result in a significantly lower complexity and shorter cycle.