On the complexity of computing tests for CMOS gates
Sourish Chakravarty · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1989
The following problems pertinent to testing CMOS gates are considered. CTSOF: the problem of computing a two-pattern test sequence that detects the fault 'T Stuck-Open' given a CMOS gate G and an FET T in G. CTSAF: the problem of computing an input vector that detects the fault in which the output of G is stuck at a given a CMOS gate G and a constant a epsilon (0, 1). It is shown that bounded degree fanout (bounded by 2) in unate CMOS gates is enough to make CTSOF CoNP-hard, CTSOF is harder than CTSAF, and an upper bound on the complexity of both CTSOF and CTSAF is O(2/sup f/*m), where f is the number of fanout variables and m is the number of FETs in the CMOS gate. It is also shown that there exists a CMOS gate realization of Boolean functions named BC-CMOS circuits such that for every Boolean function there exists a BC-CMOS circuit, there exists a linear time algorithm for both CTSOF and CTSAF for BC-CMOS circuits, and CMOS gates derived from Boolean expressions using Shannon's expansion are BC-CMOS circuits.>