Zero cost testing of check bits in RAMs with on-chip ECC
Parameswaran Ramanathan, Kewal K. Saluja, M. Franklin · 2003
The authors address the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are tested in parallel with the testing of the information bits. The solution entails finding parity-check matrices such that all the check bits are tested while the information bits are being tested, without any increase in the length of the test sequence. The resulting parity-check matrix is such that there is no loss in error-correction capabilities and with minimal penalty in the worst-case delay of the error-correcting logic.>