VLSI Design of a Wavelet Processing Core
Sze Wei Lee, Soon-Chieh Lim · IEEE Transactions on Circuits and Systems for Video Technology · 2006
A processing core architecture for the implementation of the discrete wavelet transform (DWT), optimized for throughput, scalability and programmability is proposed. The architecture is based on the RISC architecture with an instruction set specifically designed to facilitate the implementation of wavelet-based applications and a memory controller optimized for the memory access pattern of DWT processing