A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture
Narumi Sakashita, Yoriaki Nitta, Kenkichi Shimomura, F. Okuda, H. Shimano, S. Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinichi Baba, Shinji Komori, Kazuo Kyuma, A. Yasuoka, H. Abe · IEEE Journal of Solid-State Circuits · 1996
This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 /spl mu/m/sup 2/ cell and 581.8 mm/sup 2/ small die area are achieved using 0.15-/spl mu/m CMOS technology. The /spl times/61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.