A high-speed and decentralized arbiter design for NoC
Yun-Lung Lee, Jer Min Jou, Yen‐Yu Chen · 2009
As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and decentralized round-robin arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters, the HDRA design, based on a de-centralized structure, is fast with only O(log4N) in critical path delay, area-efficient, and fair. The design results of it show that the arbitration performance of the HDRA is best compared with all existing arbiters, and still has smaller area cost. This new arbiter is being applied for a patent of the ROC (application No.: 0971xxxxx).