Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
Patrick R. Schaumont, Henry Kuo, Ingrid M.R. Verbauwhede · Proceedings - ACM IEEE Design Automation Conference · 2002
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mw of power consumption. We discuss how the high level reference specification in C is translated into a parallel architecture. Design decisions are motivated from a system level viewpoint. The prototyping setup is discussed.