3D graphics tile-based systolic scan-conversion
Dan Crisu, Simon Vassiliadis, Sorin Cotöfană, Petri Liuha · 2005
A 3D graphics systolic scan-conversion unit is presented that solves existing problems associated with tile-based hardware rasterization algorithms. In our proposal no searching overhead is needed to find the first hit position inside the primitives. Furthermore "ghost" primitives are handled efficiently with a small constant delay irrespective of the primitive size. Finally, hit positions (communicated in a spatial pattern to increase texture cache hit ratios) can always be mapped to different memory banks in the Z-buffer or color-buffer breaking the "read-modify-write" dependency associated with depth test and color blending. Hardware synthesis in a commercial 0.18 /spl mu/m process technology has indicated that the hardware implementation requires an area of 269964 /spl mu/m/sup 2/, it can be clocked at a frequency of 200 MHz and consumes 33 mW. The rendering and the fill rate achieved are 2.4 million triangles/s and 460 million pixels/s for graphics scenes with typical average triangle area of 160 pixels.