Unified decoder architectures for repeat-accumulate and LDPC codes
Mohammad M. Mansour · 2005
This paper investigates the design of high-performance decoder architectures for two promising codes-repeat-accumulate (RA) and LDPC codes-of large block length, in both regular and irregular forms. It addresses the decoder implementation complexity problem for such codes that stems from the "unstructured" nature of the code's underlying Tanner graph. To decouple the complexity of the decoder from the randomness of the code structure, we extend our earlier results on LDPC codes in M. M. Mansour et al., (2003) to RA codes and identify an architecture-aware (AA) graph structure that induces regularity features amenable to efficient and scalable decoder implementations. Design methods of AA-RA codes with structured graphs for which an iterative decoding algorithm performs well under message-passing are analogous to those for AA-LDPC codes. A unified decoder architecture capable of decoding both AA-RA and LDPC codes based on the staggered decoding schedule of M. M. Mansour et al. (2003) is introduced. Architectural optimizations that address the latency, memory overhead and implementation complexity problems typical of iterative decoders for long codes are also investigated.