Multistage interconnection networks for k/n rate Viterbi decoders
David Akopian, Jarmo Takala, Jaakko T. Astola, Jukka P. P. Saarinen · 2002
New parallel architectures are proposed for Viterbi (1967) decoders with the possibility of a trade-off between the complexity and the speed. This work generalizes the design of decoders with a code rate of 1/n reported for k/n rate codes corresponding to high radix systems with the number of states N=r/sup n/, r>2. Two different solutions are given. Finally, the family of architectures is derived systematically for the general case of k/n rate codes.