A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation
Marcos Martı́nez-Peiro, Javier Valls, Trini Sansaloni, A.P. Pascual, Eduardo Boemo · 2003
In this paper, several bit-serial, high-order implementations of cascade, lattice and direct-form FIR filters using Distributed Arithmetic (DA) are studied. Although lattice and cascade structures present many interesting properties related to quantification error and stability, the DA versions have not been thoroughly compared. Three types of filters with their particular bit-serial DA model error have been built using an ALTERA 10K50 FPGA and their area-time figure is analysed. The results show that a 60th order bit-serial cascade and direct-form implementation at nearly 4 MHz and a 40th order lattice structure at 7.5 MHz can be implemented. Moreover, the lattice filter presents the lower quantification error.