Double {0, 1, 2} representation modulo-(2 n − 3) adders
Hamed Fatemi, Ghassem Jaberipur · International Conference on Systems, Signals and Image Processing · 2014
Excess-(2n − 1) representation of zero in modulo-(2n − 1) adders has led to some speed up and area/power savings, while the corresponding ripple carry realizations save additional area and power. Likewise, we propose excess-(2n − 3) representations of values {0, 1, 2}, as well as normal representations, and design the corresponding ripple carry modulo-(2n − 3) adder with 30% lower area than the hypothetical ripple carry version of the best previous relevant adders in terms of cost. We also propose a modified version with slight area and delay overhead that accepts both operands with excess-(2n − 3) representations. Such adder is required when the modulo-(2n − 3) residue generator uses the proposed double representation adder for lower cost/power. Synthesis results show that our new adders are advantageous in one or more figures of merit.