A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing
Brucek Khailany, Ted E. Williams, Jim Lin, Eileen Peters Long, Mark Rygh, D. Tovey, William J. Dally · IEEE Journal of Solid-State Circuits · 2008
A 34-million transistor stream processor system-on-chip (SoC) for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores, and I/Os. Implemented in a 0.13mum CMOS technology, sixteen 800 MHz data-parallel lanes combine to deliver performance of 512 8-bit GOPS or 256 16-bit GOPS, or 128 billion 16-bit multiply-accumulates per second GMACs), with a power efficiency of 82 pJ/MAC.