Current testability analysis of feedback bridging faults in CMOS circuits
Miquel Roca, Antonio Rubio · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1995
An exhaustive classification of bridging faults between pairs of logic level circuit nodes and an I/sub DDQ/ testability analysis scheme for these faults are presented in this paper. The case of feedback bridging faults producing oscillations is considered in detail. The testability of such faults is verified through a set of experiments with specially implemented ASIC's.>