ESTIMATING THE QUALITY OF MANUFACTURED DIGITAL SEQUENTIAL CIRCUITS
D.V. Das, Sharad C. Seth, Vishwani D. Agrawal · 2005
Abstract: Detection of a fault in a sequential circuit requires a sequence of test vectors. This se-quence activates the fault and propagates the effect of the fault to a primary output. To accomplish this, the test sequence must set flip-flops through a series of states. Unlike a combinational circuit, many faults in a sequential circuit cannot be detected by a sin-, gle vector. We propose a statistical model in which. a fault is characterized by two parameters: a per-vector detection probability and an integer-valued la-. tency. Irrespective of its detection probability, the fault cannot be detected by a vector sequence shorter than the latency. A joint distribution of the latency and detection probability over all the failed chips is thus obtained. Using the new model, an analysis o:f chip failure data to predict actual yield and reject ra-tio is given. For a large-volume CMOS chip, tested by vectors having 99.7 % fault coverage, this analysis gives a reject ratio of 43 parts per million that is be-lieved to be in close agreement with the field data. 1