FPGA implementation of a GF(2/sup 4M/) multiplier for use in pairing based cryptosystems
Maurice Keller, Tim Kerins, William Peter Marnane · 2005
In this paper an architecture for GF(2/sup 4m/) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.