Synthesis of Fully Testable Circuits From BDDs
Rolf Drechsler, Junhao Shi, Görschwin Fey · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004
We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.