End-to-end testing for boards and systems using boundary scan
R.W. Barr, Chen-Huan Chiang, E.L. Wallace · 2002
ICs with IEEE 1149.1 boundary scan (BS) Architecture have been widely used in board level design to increase the testability. An end-to-end test methodology that utilizes BS architecture for testing boards and systems throughout the product life cycle is proposed. The proposed test methodology includes a programmable dynamic BS test architecture and a series of test modules that take advantage of the test architecture for complete fault coverage. Proposed design-for-testability (DFT) techniques guarantee the co-existence of BS resting with other system functions, such as in-system programming and DSP JTAG emulation. At board level, programmable dynamic scan chains are used in a divide-and-conquer fashion to increase the flexibility in the development phase (or design verification testing, DVT). Besides, since the DFT techniques are programmable they can be used as design-for-diagnosis to increase diagnosis resolution during DVT. Address scan port chips are used to enable multi-drop test bus architecture for backplane testing as well as system embedded testing. Other advanced techniques, such as analog subsystem testing and board-level built-in self-test, as well as how to re-use BS architecture in in-circuit testing and manufacture testing are also parts of the proposed methodology that takes advantage of BS architecture to provide full scale testing for systems.