Algorithm and architecture optimization for full-mode encoding of H.264/AVC intra prediction
Chen‐Han Tsai, Yu‐Wen Huang, Liang‐Gee Chen · 2005
In this paper, we designed a four-parallel intra prediction architecture applied with four optimization schemes. Category-level interleaved scheme (CLIS) eliminates the bubble cycles of 14MB reconstruction. Mode-level scheduling (MLS) and early data preparation scheme (EDPS) rearrange the processing sequence of intra modes. The hardware resource of earlier low-complexity modes is used to deal with the computation of later high-load modes. Not only the hardware utilization is increased but the processing cycles is reduced. Furthermore, stage-level partial distortion elimination (SLPDE) is induced to skip the calculation of unnecessary intra modes. The architecture has been integrated into an H.264/AVC baseline encoder for HDTV applications and has been verified to be feasible under system consideration.