Verification of ASIC designs in VHDL using computer-aided reasoning
Edward P. Stabler, Michael P. Nassif, Robert J. Paragi · 2002
The paper describes verification of a 32-bit processor chip using formal reasoning. The VHSIC Hardware Description Language (VHDL) code for the processor and its components have been proven to meet the formal specification which uncovered interesting specification ambiguities and design errors. The paper provides an early evaluation of the role of formal reasoning in the verification of VHDL designs of practical size.