A systolic vector quantization processor for real-time speech coding
Peter R. Cappello, Grant A. Davidson, A. Gersho, Çetin Kaya Koç, V. Srinivasa Somayazulu · 2005
The architecture and implementation of a novel VLSI bit-level systolic Vector Quantization processor is described. This architecture offers very high data throughput for real-time processing applications. Given a codebook of sizeNand dimensionk, an input vector can be quantized everyNclock cycles, compared to O(kN) cycles for a Single-Instruction, Single-Data (SISD) machine. Any distortion measure which can be expressed as a Euclidean vector inner product can be computed with this array.