A Massively Parallel, Micro-grained VLSI Architecture
R.S. Bajwa, Robert Michael Owens, M.J. Irwin · 2005
This paper describes the design and implementation,al aspects of a high performance micro-grained architecture with enhanced communication capability. This architecture is capable of teraops performance. The architecture is organized as a semi-systolic array of processors. A prototyping system for the architecture which will provide control, I/O, and an interface to a host system for the micro-grained architecture is specified. Beyond the research outlined here, the prototyping system can be used as a ‘?est-bed” for various clnss/siirdent VLSI design projects. This architecture will be useful for solaing a number of important problems, such as: edge detection, locating connected components, two-dimensional signal and image processing, sorting elements, and performing element permut a t i o 71.s.