Performance modeling and characterization of large last level caches
Parijat Dube, M. Tsao, Li Zhang, Alan Bivens · 2012
Different workloads exhibit different memory footprint and have different dependency on the size and configuration of the memory subsystem. To quantify the performance implication of various memory system architectures and attributes one needs to understand the program behavior of the workload and its use of the memory subsystem. We developed the large cache simulator (LCS) to study cache performance of different applications and its sensitivity to different architecture parameters. The LCS is a multi-processor system that runs applications with a coherently attached FPGA which can emulate different cache configurations for long periods of time. The LCS measures different statistics associated with cache performance which are then used to develop cache performance models. Our goal is to explicitly characterize the performance of large last level cache for different workloads and model its dependency on cache configuration parameters.