An investigation of memory latency reduction using an address prediction buffer
A. Billingsley · Calhoun: The Naval Postgraduate School Institutional Archive (Naval Postgraduate School) · 1992
Developing memory systems to support high speed processes is a major challenge to computers architects. Cache memories can improve system performance but the latency of main memory remains a major penalty for a cache-miss. A novel approach to improve systems performance is the use of a memory prediction buffer. The memory prediction buffer (MPB) is inserted between the cache and main memory. The MPB predicts the next cache-miss address and pre-fetches the data. The use of an MPB in a computer system is shown to decrease main memory latency and increase system performance.