A quasi-floating point algorithm for combinational logic
Xinggan Zhang, Zhaoda Zhu · 2002
In this paper, a quasi-floating point algorithm is presented that is implemented with a combinational logic circuit for processing data at high speed in real-time. It is an approximate algorithm for computing module of a complex datum and nonlinear mapping of data. The circuit of quasi-floating point computing consists of normalizing unit, simple combinational logic computing unit and fixed-point restoring unit. If the remaining bit number N is 8, the relative error is less than 0.01.