Bus-based COMA-reducing traffic in shared-bus multiprocessors
Anders Landin, Fredrik Dahlgren · 2002
A problem with bus-based shared-memory multiprocessors is that the shared bus rapidly becomes a bottleneck in the machine, effectively limiting the machine size to somewhere between ten and twenty processors. We propose a new architecture, the bus-based COMA (BB-COMA) that addresses this problem. Compared to the standard UMA architecture, the BE-COMA has lower requirements on bus bandwidth. We have used program-driven simulation to study the two architectures running applications from the SPLASH suite. We observed a traffic reduction of up to 70% for BB-COMA, with an average of 46%, for the programs studied. The results indicate that the BB-COMA is an interesting candidate architecture for future implementations of shared-bus multiprocessors.