High-speed bus arbiter for multiprocessors
A. Kovaleski · IEE Proceedings E Computers and Digital Techniques · 1983
Shared-bus interconnection schemes normally suffer from insufficient capacity. Increasing their bandwidth reduces the problem but makes bus arbitration somewhat difficult. This paper presents a fair bus-arbiter design, its implementation and simulation results. Although the techniques originated from the particular constraints of the architecture considered, it is generally applicable to high-speed arbitration problems and has a low hardware cost.