A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
Achim Rettberg, Mauro C. Zanella, Christophe Bobda, Thomas Lehmann · 2003
Area minimization, low power and high performance are objectives to be reached in chip design. Bit-serial architecture offers a great advantage in comparison with bit-parallel architectures as regards area minimization. One field of application of such an architecture is e.g. signal processing in terms of digital filters or digital controllers. These algorithms may be realized in hardware by means of the proposed architecture; this requires only small chip area and an equally small number of input and outputs pins, thus reducing the size and the complexity of the printed circuit. The speed of the bit-serial processing is high enough for the application domain in question. E.g., in an electrical motor-current control there are the delays of input/output converters (e.g., A/Ds and D/As) and those resulting from the inertia of the motor.