A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems
Byeong‐Gyu Nam, Hoi‐Jun Yoo · Proceedings of ESSCIRC · 2007
A low-power, high-performance 4-way 32-bit vector processor is developed for handheld 3D graphics systems. It contains a floating-point unified matrix, vector, and elementary function unit. By utilizing the logarithmic arithmetic, the unit achieves single-cycle throughput for all these operations except for the matrix-vector multiplication with 2-cycle throughput. The processor featured by this function unit, cascaded integer-float datapath, reconfiguration of datapath, operand forwarding in logarithmic domain, and vertex cache takes 9.7mm2in 0.18μm CMOS technology and achieves 141Mvertices/s for geometry transformation and 12.1Mvertices/s for OpenGL transformation and lighting at 200MHz with 86.6mW power consumption.