A Multi-Core SoC Design for Advanced Image and Video Compression
A. Dehnhardt, Mark B. Kulaczewski, Lars Friebe, Sören Moch, P. Pirsch, H.-J. Stolberg, Carsten Reuter · 2006
A flexible SoC architecture and its hardware implementation targeting advanced MPEG-4 video coding and region-of-interest detection (ROI) is presented. The multi-core architecture integrates three fully programmable processor cores and various interfaces onto a single chip, all tied to a 64-bit AMBA AHB bus. The processor cores are individually optimized to different computational characteristics, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The SoC is fabricated in a 0.18 /spl mu/m 6LM standard-cell technology, occupies about 82 mm/sup 2/, and operates at 145 MHz. A surveillance application example includes a MPEG-4 Simple Profile encoder with preceding ROI detection for superior compression results in full TV resolution.