On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM
Satoru Tanoi, Y. Tokunaga, T. Tanabe, Kunimasa Takahashi, Akira Okada, Mitsuru Itoh, Y. Nagatomo, Y. Ohtsuki, M. Uesugi · IEEE Journal of Solid-State Circuits · 1997
An on-wafer built-in self-test (BIST) technique has been developed to implement a 200 Gb/s failed-bit search for a 1-Gb DRAM. The BIST circuits include a 4-kb very-long word bus and an on-wafer test management unit to probe DRAM arrays and compress test results. The 1-Gb DRAM is fabricated as a test device using a 0.16-/spl mu/m CMOS technology. As a result, the BIST reduces the wafer test time to less than 1/100 that of bit-by-bit testing.