A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE
Frederik Naessens, Veerle Derudder, Hans Cappelle, Lieven Hollevoet, Prasanth Raghavan, M. Desme, A.M. AbdelHamid, Ilse Vos, L. Folens, S. O'Loughlin, S. Singirikonda, Steven Dupont, Jan-Willem Weijers, Antoine Dejonghe, Liesbet Van der Perre · 2010
This paper describes the implementation of a flexible Turbo and LDPC outer modem engine which is capable of supporting the WiFi(802.11n), WiMax(802.16e) and 3GPPLTE standard on the same hardware resources. The chip is implemented in a 65nm CMOS technology and occupies 10.37 mm2. The decoder flexibility is offered by means of an application-specific instruction-set processor (ASIP), with full datapath reuse between Turbo and LDPC decoding. The encoders are dedicated ASIC datapaths. The maximum clock speed can be set to 320 MHz allowing a decoder output rate for a single iteration in excess of 140 Mbps for Turbo and 640 Mbps for LDPC with a maximum power consumption of 675 mW. The architecture template has been extended to support other standards like the DVB-S2/T2 LDPC decoding as well.