Designing a high speed decoder for cyclic codes
A. M'sir, F. Monteiro, A. Dandache, B. Lepley · International On-Line Testing Symposium · 2004
This paper proposes a new parallel implementation scheme to increase the bit rate of a cyclic code decoder. The principle is based on the partition of the architecture into a syndrome calculation block and an error accumulation block, in order to eliminate the error decision function from the feedback loop in the cyclic code decoder. This approach allows effective parallel and pipelining techniques to be applied. The resulting high speed parallel architecture has been implemented on FPGA devices from the Altera/Flex10KE family. Bit rates up to 6.8 Gbits/s have been achieved with parallelism level up to 31.