Generation of compact delay tests by multiple path activation
Soumya Bose, Rahul Agrawal, Vishwani D. Agrawal · 2002
We use a 23-value logic system to generate robust path delay tests. Each test is successively augmented to detect as many path faults as possible. Other features of the test generator are a podem-like branch and bound search for test, an efficient path designation based on ordering of paths, and an algorithmic selection of secondary target faults for augmenting the tests to cover multiple faults. Results for ISCAS '89 benchmarks are given.>