SYNTEST: an environment for system-level design for test
HAIDAR M. HARMANANI, C. Papachristou, S. Chiu, Mehrdad Nourani · 1992
This paper describes the design and implementation of SYNTEST, a system for the design of self-testable VLSI circuits from behavioral description. SYNTEST consists of several algorithmic synthesis tools for scheduling, testable allocation, and optimum test points selection. A key feature in SYNTEST is the tight intercation between the system tools: the scheduler, the allocator, and the test tool. The system uses a technology library for optimizing the original structure. All tools interact with each other as well with the user through an X graphical interface. This provides a better design environment and allows for more designer intervention. 1 Introduction Design and Test are commonly viewed as being two sides of the same coin [2]; due to the complexity in current VLSI technology, both processes are partitioned into corresponding hierarchical levels. Three well defined top-down levels of the design and test hierarchy are the system (RTL), the logic gate, and the layout levels. The ...