Comparison of binary full adder and quaternary signed-digit full adder using high-speed ECL
Fumio Wakui, Masamitsu Tanaka · 2003
Details are presented of the algorithm and the several circuits needed to construct a novel emitter-coupled logic (ECL) quaternary signed-digit full adder (SDFA/sub 4/) to realize high-speed operation under restrained power dissipation. To reduce the circuit size, the input part of the SDFA/sub 4/ which converts the sums of input currents to voltage signals, detects the signs of the sums. The output part, which has the unsigned transfer characteristic, selects output lines corresponding to the signs. To increase the maximum number of realizable thresholds under the restrained supply voltage of the ECL, a signal distributor was used. The SDFA/sub 4/ performance is compared to that of a 4-b carry-lookahead full adder.>