A mixed mode neuro-VLSI chip for high speed applications
Khurram Waheed, F.M. Salam · 2002
This paper presents selected design and operation details of a custom integrated neural chip. This neural processing chip is designed in the recent 0.18 /spl mu/m, single poly, six-layer Cu interconnect technology. The chip realizes an architecture that achieves the task of autonomous-learning execution times in micro to milli seconds. The core consists of basic building blocks of 4-quadrant multipliers, transconductance amplifiers, and active load resistances, for analog (forward) network processing and learning modules. Super-imposed on the processing network are digital memory and control modules composed of D-Flipflops, ADC, Multiplying D/A Converter (MDAC), decoders, multiplexers and comparators for parameter (weight) storage, logical control and analog/digital conversions.