A low power consumption BIST testing technology based on heavy input
Yi Wang · 2009
This paper introduces a lower power built-in-self-test technology, which can effectively reduce the average power consumption of under-test circuits during testing. Its basic theory is to improve the structure of test vector generator using ldquoAND/NOrdquo gate tree, therefore decreasing the turn time of ldquoimportant inputrdquo end among under-test circuits to reduce power consumption. The result of Benchmark experiment circuit emulation indicates this method may gain higher test efficiency, and it's suitable for BIST of digital integrated circuits especially.