A compact AES encryption core on Xilinx FPGA
Dur‐e‐Shahwar Kundi, Saleha Zaka, Qurat‐ul‐Ain, Arshad Aziz · 2009
This paper presents an Advanced Encryption Standard (AES) encryption core on Field Programmable Gate Array (FPGA). The target device is Spartan-3 FPGA. We have designed an efficient and compact, iterative architecture with input and key, both of 128 bits. The throughput achieved is 2640.3712 Mbps with a frequency of 206.28 MHz; using 8 embedded Block RAMs (BRAMs) and 390 Slices. The aim is to provide a fast encryption core for small size and low cost applications.