On-Chip Interconnection Architecture of the Tile Processor
David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, B. Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown, Anant K. Agarwal · IEEE Micro · 2007
IMesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. taking advantage of the five networks, the C-based ILIB interconnection library efficiently maps program communication across the on-chip interconnect. the tile processor's first implementation, the tile64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 Ghz.