The arithmetic cube II: a second generation VLSI DSP processor
M.J. Irwin, Robert Michael Owens, Thomas P. Kelliher, Kwong-Keung Leung, Mohan Vishwanath · 1991
A description is given of the synthesis, design, and simulation of the arithmetic cube II, a second-generation, high-performance digital signal processing architecture. The architecture implements the so-called small-n algorithms. The authors are currently building a CMOS prototype system which should be capable of computing a 1024 point complex DFT in 410 mu s.>