A Scalable Bandwidth Aware Architecture for Connected Component Labeling
Vikram Sampath Kumar, Kevin M. Irick, Ahmed Al Maashri, N. Vijaykrishnan · 2010
Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.