Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption
Myounggon Kang, Kitae Park, Youngsun Song, Young-Ho Lim, Kang-Deog Suh, Hyungcheol Shin · Japanese Journal of Applied Physics · 2011
Two new NAND structures using double common source line (CSL) and dummy switch and their read operation schemes as a solution for NAND flash memories have been proposed. Compared with conventional scheme, the proposed read schemes improves read disturb characteristics beyond sub-30 nm technology node. By using proposed read scheme, the number of fail bits of proposed NAND was decreased than those of conventional NAND at read cycles. Also, it was proven that they contribute to improve the performance and suppress the power consumption. The proposed NAND was verified by both simulation and experimental measurements in a fabricated 40 nm multi level cell (MLC) NAND device.