SMART And FAST: Test Generation for VLSI Scan-Design Circuits
M. Abramovici, James J. Kulikowski, Prem R. Menon, David T. Miller · IEEE Design & Test of Computers · 1986
This article describes new concepts and algorithms used to generate tests for VLSI scan-design circuits. The new algorithms include: 1. a low-cost fault-independent algorithm (SMART), 2. a fault-oriented algorithm (FAST), and 3. an algorithm for dynamic test set compaction. The fault-oriented algorithm is guided by new controllability/observability cost functions whose objective is to minimize the amount of search done in test generation.